This application claims benefit of priority under 35 USC 119 to Japanese Patent Application No. P2000-295147 filed Sep. 27, 2000, the entire contents of which are incorporated by reference herein.
1. Field of the Invention
The present invention relates to a pattern writing system, algorithm of pattern data generation and method of writing a pattern layout of electronic parts. The present invention consists of an apparatus for and a method of dividing a layout area, which generally corresponds to a writing field of the pattern writing system, into small sections (fields) and dividing a pattern layout of an electronic part into small figures (shots). The pattern layout of the electronic part is formed by drawing pattern data in each section by section-by-section exposure. The present invention also relates to a storage medium storing a computer program to execute the method mentioned above with a computer system. In particular, the present invention relates to a pattern writing system like electron beam (EB) exposure system for writing patterns of a semiconductor integrated circuit, which has high-density of fine patterns. The pattern layout of the electronic device is realized by dividing the pattern layout into small figures and by dividing exposure region into small sections, and small figures within of each section is exposed section-by-section so that small figures may collectively constitute the pattern layout. The present invention also relates to any pattern writing method and algorithm of pattern data generation, which divides the pattern layout of the electronic part into small figures and divides the writing field of the pattern writing system, which can be used to write patterns of printed circuit boards or any other patterns.
2. Description of the Related Art
The minimum feature size of semiconductor is decreasing year by year according to the scaling law and fabrication of fine patterns below 100 nm is strongly required at present. Such fine patterns are out of the resolution of optical exposure systems, and electron beam exposure systems of high resolution are expected to cope with such fine patterns.
In electron beam exposure system, pattern layout of LSI is divided into small figures where one figure correspond to one beam shot of the electron beam. The size of each shot is typically of several microns, which is being determined to secure uniform electron beam intensity. The electron beam exposure system emits and electron beam to a substrate section by section, to draw continuous patterns on the substrate. Any LSI pattern or wiring pattern extending over several sections is divided into several shots and is formed on the substrate section by-section such that shot within of one section is exposed and then shots in adjacent section is exposed.
FIG. 1A shows a gate electrode pattern 51 of MOSFET as an example of a pattern formed in a layout area of an electronic part. The pattern 51 is divided into shots 52 as shown in FIG. 1B. The shots 52 in FIG. 1B are still in the form of pattern data (design data), and therefore, involve no connection errors.
Whether or not the pattern 51 is correctly drawn on a substrate by electron beam exposure is dependent on the positioning accuracy of the shots 52. If the positioning accuracy is low, the shots 52 may partly overlap or may be discontinuous.
FIG. 1C shows misalignment among the shots 52 due to positioning errors of the electron beam. These positioning errors draws a deformed gate electron 53 of FIG. 1D on a substrate after shot-by-shot electron beam exposure. If adjacent shots overlap each other, the drawn gate electrode 53 will be long at a connection between the shots. If adjacent shots are separated from each other, the drawn gate electrode 53 will be short at a connection between the shots. The long connection decreases the driving power of the MOSFET, and the shot connection increases OFF leak current. If the connection is too short and breaks, an OFF leak current increase and a driving power decrease simultaneously occur to deteriorate the performance and yield of the MOSFET.
FIG. 2 is a graph showing drain current-gate voltage (Id-Vg) curves of MOSFETs Id-Vg characteristics of a normal MOSFET without a gate electrode depicted with the curve with circles shows a steep change in drain current around a gate voltage of zero. Id-Vg characteristics of a defective MOSFET with a broken gate electrode depicted with curve with triangles shows an almost constant drain current irrespective of gate voltage. This defective MOSFET shows increase in OFF leakage current which deteriorate switching performance of MOSFET.
The most effective way to prevent the deformation of formed pattern is to improve the positioning accuracy of each beam shot. However, there is a limit in improving the beam positioning accuracy, which is mainly an issue of mechanical control of the stage and electrostatic control of the electron beam. Therefore, another approach such as pattern generation algorithm should be considered. For example, Japanese Unexamined Patent Publication Nos. 10-223508 and 9-293667 disclose techniques of setting connections of shots in isolation region when forming gate electrode patterns of MOSFETs. The main idea of these patents is to generate shot patterns of to-be-drawn gate electrode patterns to be butt-joined to each other on the isolation region. This is because deformation of gate electrode pattern on the isolation field is less sensitive to MOSFET characteristics compared to deformation of gate electrode pattern on active area.
The techniques may be easy to achieve and effective when applied to LSIs having regular patterns of fixed size such as memories. The techniques, however, are ineffective when applied to logic or analog LSIs having random patterns with different shape and size that hardly allow shot connections to be formed in element isolation regions.
Japanese Unexamined Patent Publication 2-71509 discloses a technique of providing shots with protrusions at the butting edge. The protrusions of shots sections overlap at exposure, to avoid shot-by-shot breakage or thickening. This technique needs a beam shot having the special shape that requires a special aperture or stencil mask, and therefore, is impractical for producing logic or analog LSIs consist of different patterns.
The object of the invention is to provide a pattern forming method and pattern forming apparatus in order to realize high writing accuracy, which divides writing field into small sections and write pattern data section-by-section, where the relationship between the pattern layout and the boundary of sections is considered in writing sequence.
A first aspect of the present invention provides an apparatus which prepares EB-data, comprising the step of dividing a writing field into small sections and generating a to-be-drawn pattern layout of an electronic part into small figure (shots), in order to form a desired pattern layout by exposing shots within of one section and repeating section-be-section exposure. Hereafter, we define EB-data as a general name for the data used to control the pattern writing equipment, such as pattern data (shot data) of the layout and data of sections. The apparatus includes an EB-data generator and an EB-data diagnosis unit. The EB-data generator divides the layout area (writing field) into small sections and divides the pattern layout of a circuit of an electronic part into small figures where a small figure corresponds to a single shot of the beam. The EB-data diagnosis unit detects a violation shot among the shot data that crosses a boundary between adjacent ones of the sections and has shot size L smaller than a threshold xe2x80x9ck*Laxe2x80x9d where La is a section-to-section connection allowance and k is a coefficient.
A second aspect of the present invention provides a method of preparing EB-data, comprising the step of dividing a writing field into small sections and generating a to-be-drawn pattern layout of an electronic part into small figures (shots), in order to form a desired pattern layout be exposing shots within of one section be repeating section-by-section exposure The method forms and lays the patterns in the layout area according to circuit data of the electronic part, the layout area being divided into the sections. The method detects a violation shot among the shot data that crosses a boundary between adjacent ones of the sections and has shot size L smaller than a threshold xe2x80x9ck*Laxe2x80x9d where La is a section-to-section connection allowance and k is a coefficient.
A third aspect of the present invention provides a computer program for preparing EB-data used for a process that divides a layout area of an electronic part into sections and draws patterns in the layout area section by section. The computer program executes a series of procedures to form pattern data in a layout area of an electronic part according to circuit data of the electronic part, the layout area being divided into sections, and detect a violation shot among the shot data that crosses a boundary between adjacent ones of the sections and has a shot size L smaller than a threshold xe2x80x9ck*Laxe2x80x9d where La is a section-to-section connection allowance and k is a coefficient.
A fourth aspect of the present invention provides a method of preparing EB-data, comprising:
the step of dividing a layout area of an electronic part into hierarchical sections having different predefined area ranging from level-0 to level-N, where level-0 sections are unit sections having the smallest area and level-N sections are sections having the largest area,
and hereafter, level-i sections (i being sequentially changed from 1 to N) is defined as the sections having the area size of i-th size counted up from the sections having the smallest area,
the step of generating pattern data (shot data) from the to-be-drawn layout pattern of circuit data,
the step of grouping level-(i-1) sections to groups which satisfy the shot data that crosses a boundary between adjacent ones of the sections has a shot size L smaller than a threshold xe2x80x9ck*La,ixe2x80x9d where La,i is a section-to-section connection allowance of level-i sections and k is a coefficient,
the step of forming new groups having area size below predefined area size of level-i section, which consist of level-(i-1) section groups (determined in the above step) that adjoin to each other, and redefine the new groups as level-i sections,
thereby, a desired layout pattern of the electronic part is formed by exposing the shot within of one section, section-by-section.
A fifth aspect of the present invention provides an electronic part having a layout area divided into sections. The layout area has patterns drawn section, every pattern that crosses a boundary between adjacent sections having a size L greater than a threshold xe2x80x9ck*Laxe2x80x9d where La is a section-to-section connection allowance and k is a coefficient.
A sixth aspect of the present invention provides a method of manufacturing an electronic part including designing and laying patterns in a layout area of the electronic part, dividing the layout area into sections, detecting among the patterns, a violation pattern that crosses a boundary between adjacent ones of the sections and has a size L smaller than a threshold xe2x80x9ck*Laxe2x80x9d where La is a section-to-section connection allowance and k is a coefficient, shifting the violation pattern into one of the adjacent sections, and drawing the patterns including a shifted violation patterns, in the layout area by section-by-section exposure.